The present invention relates to a pixel calculating device that has a filtering circuit for resizing images.
In recent years, remarkable technical developments have been made in relation to digital imaging equipment, and now available on the market are media processors capable, for example, of compressing, decompressing, and resizing moving images. In image resizing, finite impulse response (FIR) filters are commonly used.
FIG. 1 is a block diagram showing an exemplary prior art FIR filtering circuit. The FIR filter shown in FIG. 1 has seven taps and symmetrical coefficients. In this circuit, data inputted in time series from data input terminal 1001 is sent sequentially to delayers 1002, 1003, 1004, 1005, 1006, and 1007.
When the filter coefficients are symmetrical, tap pairings having the same coefficient value are pre-summed and then multiplied by the shared coefficient, rather than multiplying each tap individually by the coefficient. The filter coefficients are said to be in symmetry when the coefficients corresponding the input and output (i.e. xe2x80x9ctapsxe2x80x9d) from data input terminal 1001 and the delayers 1002 to 1007, respectively, are symmetrical around the center tap (i.e. the output of delayer 1004).
In the prior art FIR filter, for example, the input of data input unit 1001 and the output of delayer 1007 are summed in adder 1008 and the result is multiplied by coefficient h0 in multiplier 1008. Likewise, the output from delayers 1002 and 1006 are summed in adder 1009 and the result is multiplied by coefficient h1 in multiplier 1009. The output from multipliers 1011 to 1014 is then summed in adder 1015 and the result of the filtering is outputted in time-series from data output terminal 1016.
The value of coefficients h0 to h3 is determined by the rate of image downscaling. If the downscaling rate is xc2xd the output from adders 1008xcx9c1010 is decimated by xc2xd to obtain the downscaled image.
Symmetrical filter coefficients are preferred because of the favorable image quality resulting from the linear phase (i.e. the phase being linear with respect to frequency)
However, with the above prior art method, the configuration of the circuit dictates that the pixel data comprising the image are inputted sequentially from left to right, thus allowing only one pixel to be inputted per clock cycle.
A filtering circuit capable of fast processing speeds is also necessary if vertical downscaling is to be performed real-time with the input of frame data.
To this end, improvements in circuitry processing speeds can be accomplished by increases in operating frequency, although increasing the operating frequency adversely leads to increases in cost and power consumption.
The objective of the present invention is to provide a pixel calculating device that performs efficient and reliable multi-rate downscaling.
The pixel calculating device provided in order to achieve the above objective has (i) a decoding unit for decoding compressed video data to produce frame data, (ii) a frame memory for storing the decoded frame data, (iii) a filtering unit for vertically downscaling the decoded frame data by means of vertical filtering to produce a vertically downscaled image, (iv) a buffer memory for storing the vertically downscaled image, and (v) a control unit for controlling the filtering unit based on a state of the decoding of the video data by the decoding unit and a state of the vertical filtering of the frame data by and the filtering unit, respectively, so that overrun and underrun do not occur in the filtering unit.
In this construction, the control unit prevents the overrun and underrun of data flowing between the decoding unit and the filtering unit, and thus achieves a desirable effect without needing to introduce of a high-speed filtering unit.
The control unit receives a first notification from the decoding unit showing a state of progress of the decoding by the decoding unit. The control unit receives a second notification from the filtering unit showing a state progress of the vertical filtering by the filtering unit.
The first notification is sent from the decoding unit to the control unit after every integer multiple of the lines of the macroblock that have undergone decoding. The second notification is sent from the filtering unit to the control unit after every integer multiple of the lines of a macroblock that have undergone vertical filtering.
Thus in this construction, the control unit is able to perform effective control as a result of the first notification and the second notification being sent to the control unit after every integer multiple of the lines of a macroblock that have undergone decoding and vertically filtering, respectively.